1. Field of Invention
The present invention relates to a digital-to-analog converter (DAC). More particularly, the present invention relates to a current steering digital-to-analog converter, which can improve resolution and resolve device mismatch by using two lower-resolution digital-to-analog converters.
2. Description of Related Art
The digital-to-analog converter (referred to as DAC hereinafter) has been widely used for data conversion in electronic apparatuses. A DAC is mainly used for converting a digital signal into a corresponding analog signal, so that the analog signal can be applied to an electronic apparatus. The field whereto DAC is applied is very extensive. For example, high-resolution and high-speed DAC can be used in the communication system such as cell phone or base station, wireless communication network, image processing and display system, or audiovisual system etc.
Generally, a typical DAC is, for example, a binary-weighted DAC. A binary-weighted DAC includes various current sources and corresponding switches. FIG. 1A is a circuit diagram of a conventional binary-weighted DAC. Here a 3-bit DAC including 3 current sources 102, 104, and 106, and 3 corresponding switches S1, S2, and S3 are given as example. The current source 102 is connected to the switch S1 through wiring 112 and outputs through output wiring 118. The current source 104 is connected to the switch S2 through wiring 114 and outputs through output wiring 118. The current source 106 is connected to the switch S3 through wiring 116 and outputs through output wiring 118. The ratio of the current provided by the 3 current sources 102, 104, and 106 is 4:2:1; that is, if the current provided by the current source 106 is 1A, then the current provided by the current sources 104 and 102 are respectively 2A and 4A.
During the operation, the input code IN controls the on/off of the switches S1, S2, and S3, and the corresponding output current is output to the output terminal OUT through wiring 118. With this control, the quantity of the output current is proportional to the input code IN, and a typical output stage circuit (not shown), such as an operation amplifier, can be connected to the DAC in series to convert the output current into a corresponding voltage value, or into a low-impedance voltage output. The control circuit of this kind of binary-weighted DAC is simple.
However, some transient glitch may still occur, which may affect the accuracy of the digital-to-analog conversion, during the operation described above. For example, when the input code IN is converted from 011 (binary) to 100, all the 3 switches S1, S2, and S3 will change their status even though the value changed is only “1”. This characteristic of the binary-weighted DAC makes it inapplicable to high-resolution conversion, and it's not guaranteed to be a non-monotonic function. Referring to FIG. 1B, which is a diagram illustrating the corresponding coordinates of the input code and the differential non-linearity (DNL) error. According to the input code, large DNL error may be occur at certain intervals. That's because at two adjacent points of the conversion function of converting the digital input code IN to an analog signal, the output analog value may deviate from the ideal value. The problem of DNL error will affect the accuracy of the DAC output, or even worse, will result in very serious non-monotonic problem. The non-monotonic problem is that the output analog value corresponding to a smaller digital input code IN is greater than the output analog value corresponding to a greater digital input code IN, which may cause very serious error. It can be understood from FIG. 1C that during the data conversion process, unpredictable transient glitch may occur.
In other words, if a higher-resolution binary-weighted DAC is used, each digital bit received controls 2(n−1) current source cells. For example, for a 10-bit binary-weighted DAC, n is 1 to 10, thus, the transient glitch is very serious. The DNL error problem may be caused by different characteristics of the transistors formed in the arrangement of current source cells. The differences between the formed transistors are generally differences caused during the semiconductor fabricating process, such as difference in oxide layers, very bad polysilicon etching, or ion implant offset etc. Moreover, this kind of binary-weighted DAC takes a lot of chip layout space.
To solve the transient glitch, a thermometer code DAC is provided by those skilled in the art to control the output of the current source. Referring to FIG. 2, which is a diagram illustrating the layout of an 8-bit thermometer code DAC. The 8-bit thermometer code DAC converts the first 4 most significant bits (referred to as MSB thereinafter) into corresponding 15-bit data M1, M2, M3 . . . M15 (M1˜M15). In addition, the 8-bit thermometer code DAC converts the first 4 least significant bits (referred to as LSB thereinafter) into corresponding 15-bit data L1, L2, L3 . . . L15 (L1˜L15). The converted data is the “thermometer code” output. The thermometer code can be used for preventing transient glitch produced when the code IN is increased progressively.
The thermometer code DAC further includes 15 current source cells CSM1˜CSM15 corresponding to the MSB and 15 current source cells CSL1˜CSL15 corresponding to the LSB. The arrangements of the LSB current source cells CSL1˜CSL15 and the MSB current source cells CSM1˜CSM15 are as shown in FIG. 2. The LSB and MSB current source cells are formed by 255, including 16 columns and 16 rows, MOS transistors. Each transistor is denoted as Tij, wherein i and j represent the number of column and the number of row respectively.
In the DAC which controls current source output using thermometer code, the numbers of current source cells controlled by each thermometer code are only different by 1, thus the transient glitch can be avoided effectively. However, the current source cells required are large and the control circuit is very complicated.
To reduce the size of the required current source cells and minimize the complexity of the control circuit, a segment type DAC, which combines the thermometer code DAC and the binary-weighted DAC, is provided by those skilled in the art to control the output of the current source. Assuming a segment type DAC with N-bit digital-to-analog conversion function is used, then the first M MSB of the N-bit input code is converted with thermometer code digital-to-analog conversion. And the other N-M LSB is converted with binary-weighted digital-to-analog conversion.
Please refer to FIG. 3, which is a circuit diagram illustrating the bias generation method of a conventional current steering DAC. The bias thereof is generated by a bias generation circuit 300, which includes an operation amplifier 310, a transistor 320, and a resistor 330. The current generated is Vref/R, the unit current thereof is Vref/(R*X), wherein R is the resistance of the resistor 330, and X is the magnification power of the transistor 320. As long as the sizes of all the transistors 340, for example, P-type metal oxide semiconductors (referred to as PMOS thereinafter), in the current source cells of the thermometer code portion of the MSB and the current source cells of the binary-weighted portion of the LSB are the same, the purpose of weighting, and further the purpose of controlling the output current, can be achieved by controlling only the number of PMOS.
For example, if a 10-bit DAC is a binary-weighted DAC, then the binary weights are 512, 256, 128, 64, 32, 16, 8, 4, 2, and 1, and 1023 PMOS transistors are required. If it is a DAC combining the thermometer code DAC and the binary-weight DAC, then the thermometer code portion is 64*15, and the binary-weight portion is 32, 16, 8, 4, 2, and 1; that is, (64*15, 32, 16, 8, 4, 2, 1), which is 1023, PMOS transistors are required.
The structure of this kind of current steering DAC, regardless of binary-weight type or the combination of thermometer code type and binary-weight type, requires 1023 current source cells. Thus a lot of chip area is consumed and the circuit layout becomes too complicated. In addition, the difference in circuit layout may result in mismatch between current source cells. And the mismatch between current source cells may worsen the linearity characteristic of the DAC, or even cause the aforementioned problem of non-monotonic function. The main reason for the mismatch between current source cells is device mismatch, which is due to device variation during the manufacturing process, and the problem can be improved by using appropriate layout, but can not be eliminated. For example, if the distances between current source cells and the output terminal are different and the differences are compensated with metal wire, then the surface area of the entire current cell array is enlarged, which is against the present trend of reducing chip area.
The chip area will become smaller and smaller in consideration of manufacturing cost and future application. And this is also another reason for the mismatch problem. Since the sizes of devices are getting smaller, to reduce the chip area, the layout limitation is getting stricter, so that the connecting wires of the devices in the chip are strictly restricted.
As a result, the higher the requirement of the DAC to the resolution, the more serious the device mismatch problem.